• Russ Anderson's avatar
    [IA64] Update processor_info features · 895309ff
    Russ Anderson authored
    Add the printing of additional processor features to proc_features.
    
    Based on Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software
    Developer's Manual" (January 2006) fields (pages 2:430-2:432).
    This patch gets the features back in sync with the spec.
    
    Sample output before:
    --------------------------------------------------------------
    cobra:~ # cat /proc/pal/cpu0/processor_info
    XIP,XPSR,XFS implemented                 : On NoCtrl
    XR1-XR3 implemented                      : On NoCtrl
    Disable dynamic predicate prediction     : NotImpl
    Disable processor physical number        : NotImpl
    Disable dynamic data cache prefetch      : NotImpl
    Disable dynamic inst cache prefetch      : NotImpl
    Disable dynamic branch prediction        : NotImpl
    Disable BINIT on processor time-out      : On Ctrl
    Disable dynamic power management (DPM)   : NotImpl
    Disable coherency                        : NotImpl
    Disable cache                            : NotImpl
    Enable CMCI promotion                    : Off Ctrl
    Enable MCA to BINIT promotion            : Off Ctrl
    Enable MCA promotion                     : NotImpl
    Enable BERR promotion                    : NotImpl
    cobra:~ #
    --------------------------------------------------------------
    
    Sample output after:
    --------------------------------------------------------------
    cobra:~ # cat /proc/pal/cpu0/processor_info
    Unimplemented instruction address fault  : NotImpl
    INIT, PMI, and LINT pins                 : NotImpl
    Simple unimplimented instr addresses     : On NoCtrl
    Variable P-state performance             : NotImpl
    Virtual machine features implemeted      : On NoCtrl
    XIP,XPSR,XFS implemented                 : On NoCtrl
    XR1-XR3 implemented                      : On NoCtrl
    Disable dynamic predicate prediction     : NotImpl
    Disable processor physical number        : NotImpl
    Disable dynamic data cache prefetch      : NotImpl
    Disable dynamic inst cache prefetch      : NotImpl
    Disable dynamic branch prediction        : NotImpl
    Disable P-states                         : Off Ctrl
    Enable MCA on Data Poisoning             : Off Ctrl
    Enable vmsw instruction                  : On Ctrl
    Enable extern environmental notification : NotImpl
    Disable BINIT on processor time-out      : On Ctrl
    Disable dynamic power management (DPM)   : NotImpl
    Disable coherency                        : NotImpl
    Disable cache                            : NotImpl
    Enable CMCI promotion                    : Off Ctrl
    Enable MCA to BINIT promotion            : Off Ctrl
    Enable MCA promotion                     : NotImpl
    Enable BERR promotion                    : NotImpl
    cobra:~ #
    --------------------------------------------------------------
    
    Signed-off-by: Russ Anderson (rja@sgi.com)
    Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
    895309ff
palinfo.c 25.3 KB