• Imre Deak's avatar
    drm/i915/tgl+: Add locking around DKL PHY register accesses · 89cb0ba4
    Imre Deak authored
    Accessing the TypeC DKL PHY registers during modeset-commit,
    -verification, DP link-retraining and AUX power well toggling is racy
    due to these code paths being concurrent and the PHY register bank
    selection register (HIP_INDEX_REG) being shared between PHY instances
    (aka TC ports) and the bank selection being not atomic wrt. the actual
    PHY register access.
    
    Add the required locking around each PHY register bank selection->
    register access sequence.
    
    Kudos to Ville for noticing the race conditions.
    
    v2:
    - Add the DKL PHY register accessors to intel_dkl_phy.[ch]. (Jani)
    - Make the DKL_REG_TC_PORT macro independent of PHY internals.
    - Move initing the DKL PHY lock to a more logical place.
    
    v3:
    - Fix parameter reuse in the DKL_REG_TC_PORT definition.
    - Document the usage of phy_lock.
    
    v4:
    - Fix adding TC_PORT_1 offset in the DKL_REG_TC_PORT definition.
    
    Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Cc: Jani Nikula <jani.nikula@intel.com>
    Cc: <stable@vger.kernel.org> # v5.5+
    Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20221025114457.2191004-1-imre.deak@intel.com
    89cb0ba4
intel_display_power_well.c 57.9 KB