• Will Deacon's avatar
    sparc32: mm: Restructure sparc32 MMU page-table layout · 8e958839
    Will Deacon authored
    The "SRMMU" supports 4k pages using a fixed three-level walk with a
    256-entry PGD and 64-entry PMD/PTE levels. In order to fill a page
    with a 'pgtable_t', the SRMMU code allocates four native PTE tables
    into a single PTE allocation and similarly for the PMD level, leading
    to an array of 16 physical pointers in a 'pmd_t'
    
    This breaks the generic code which assumes READ_ONCE(*pmd) will be
    word sized.
    
    In a manner similar to ef22d8ab ("m68k: mm: Restructure Motorola
    MMU page-table layout"), this patch implements the native page-table
    setup directly. This significantly increases the page-table memory
    overhead, but will be addresses in a subsequent patch.
    
    Cc: "David S. Miller" <davem@davemloft.net>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Signed-off-by: default avatarWill Deacon <will@kernel.org>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    8e958839
pgalloc_32.h 1.85 KB