• Fernando Guzman Lugo's avatar
    ARM: OMAP2+: hwmod: add softreset delay field and OMAP4 data · d99de7f5
    Fernando Guzman Lugo authored
    Due to HW limitation, some IPs should not be accessed just after a
    softreset. Since the current hwmod sequence is accessing the sysconfig
    register just after the reset, it might lead to OCP bus error in
    that case.
    
    Add a new field in the sysconfig structure to specify a delay in usecs
    needed after doing a softreset.
    
    In the case of the ISS and FDIF modules, the L3 OCP port will be
    disconnected upon a SW reset. That issue was confirmed with HW simulation
    and an errata should be available soon. The HW recommendation to avoid
    that is to wait for 100 OCP clk cycles, before accessing the IP.
    
    Considering the worse case (OPP50), the L3 bus will run at 100 MHz,
    so a 1 usec delay is needed. Add an x2 margin to be safe.
    Acked-by: default avatarBenoit Cousson <b-cousson@ti.com>
    Signed-off-by: default avatarFernando Guzman Lugo <fernando.lugo@ti.com>
    [paul@pwsan.com: dropped FDIF change for now since the hwmod data is not
     yet upstream; the FDIF change will need to be added later once the FDIF
     data is merged]
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    d99de7f5
omap_hwmod.h 21.9 KB