• Dan Williams's avatar
    [ARM] xsc3: fix xsc3_l2_inv_range · c7cf72dc
    Dan Williams authored
    When 'start' and 'end' are less than a cacheline apart and 'start' is
    unaligned we are done after cleaning and invalidating the first
    cacheline.  So check for (start < end) which will not walk off into
    invalid address ranges when (start > end).
    
    This issue was caught by drivers/dma/dmatest.
    
    2.6.27 is susceptible.
    
    Cc: <stable@kernel.org>
    Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
    Cc: Lothar WaÃ<9f>mann <LW@KARO-electronics.de>
    Cc: Lennert Buytenhek <buytenh@marvell.com>
    Cc: Eric Miao <eric.miao@marvell.com>
    Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
    c7cf72dc
cache-xsc3l2.c 4.16 KB