It is clearly stated on "Loongson 3A3000/3B3000 processor
user manual vol 2" that

"All access requests using a non-cached algorithm are executed in a
blocking order. That is, before the current read request data is
returned to the processor, all subsequent requests are blocked and issued;
All subsequent requests are blocked until the write request data has been
sent or the issued write request has not received a write reply from the
final receiver."

Which means uncached read/write is strongly ordered. So we won't need this
workaround.

This option was introduced when we add initial support for GS464E, it looks
like a misinterpretation of another section in the manual saying we need
barriers to ensure MMIO order against DMA requests.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>