• Serge Semin's avatar
    mips: Add CONFIG/CONFIG6/Cause reg fields macro · 999079c8
    Serge Semin authored
    There are bit fields which persist in the MIPS CONFIG and CONFIG6
    registers, but haven't been described in the generic mipsregs.h
    header so far. In particular, the generic CONFIG bitfields are
    BE - endian mode, BM - burst mode, SB - SimpleBE, OCP interface mode
    indicator, UDI - user-defined "CorExtend" instructions, DSP - data
    scratch pad RAM present, ISP - instruction scratch pad RAM present,
    etc. The core-specific CONFIG6 bitfields are JRCD - jump register
    cache prediction disable, R6 - MIPSr6 extensions enable, IFUPerfCtl -
    IFU performance control, SPCD - sleep state performance counter, DLSB -
    disable load/store bonding. A new exception code reported in the
    ExcCode field of the Cause register: 30 - Parity/ECC error exception
    happened on either fetch, load or cache refill. Lets add them to the
    mipsregs.h header to be used in future platform code, which have them
    utilized.
    Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
    Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
    Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
    Cc: Paul Burton <paulburton@kernel.org>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: Arnd Bergmann <arnd@arndb.de>
    Cc: Rob Herring <robh+dt@kernel.org>
    Cc: devicetree@vger.kernel.org
    Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
    999079c8
mipsregs.h 94 KB