• Matt Roper's avatar
    drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr · 9a92732f
    Matt Roper authored
    Although all DSS belong to a single pool on Xe_HP platforms (i.e.,
    they're not organized into slices from a topology point of view), we do
    still need to pass 'group' and 'instance' targets when steering register
    accesses to a specific instance of a per-DSS multicast register.  The
    rules for how to determine group and instance IDs (which previously used
    legacy terms "slice" and "subslice") varies by platform.  Some platforms
    determine steering by gslice membership, some platforms by cslice
    membership, and future platforms may have other rules.
    
    Since looping over each DSS and performing steered unicast register
    accesses is a relatively common pattern, let's add a dedicated iteration
    macro to handle this (and replace the platform-specific "instdone" loop
    we were using previously.  This will avoid the calling code needing to
    figure out the details about how to obtain steering IDs for a specific
    DSS.
    
    Most of the places where we use this new loop are in the GPU errorstate
    code at the moment, but we do have some additional features coming in
    the future that will also need to loop over each DSS and steer some
    register accesses accordingly.
    Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
    Reviewed-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20220701232006.1016135-1-matthew.d.roper@intel.com
    9a92732f
intel_engine_cs.c 61.5 KB