• Suresh Siddha's avatar
    x86, pat: Allow ISA memory range uncacheable mapping requests · 1adcaafe
    Suresh Siddha authored
    Max Vozeler reported:
    >  Bug 13877 -  bogl-term broken with CONFIG_X86_PAT=y, works with =n
    >
    >  strace of bogl-term:
    >  814   mmap2(NULL, 65536, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0)
    >				 = -1 EAGAIN (Resource temporarily unavailable)
    >  814   write(2, "bogl: mmaping /dev/fb0: Resource temporarily unavailable\n",
    >	       57) = 57
    
    PAT code maps the ISA memory range as WB in the PAT attribute, so that
    fixed range MTRR registers define the actual memory type (UC/WC/WT etc).
    
    But the upper level is_new_memtype_allowed() API checks are failing,
    as the request here is for UC and the return tracked type is WB (Tracked type is
    WB as MTRR type for this legacy range potentially will be different for each
    4k page).
    
    Fix is_new_memtype_allowed() by always succeeding the ISA address range
    checks, as the null PAT (WB) and def MTRR fixed range register settings
    satisfy the memory type needs of the applications that map the ISA address
    range.
    Reported-and-Tested-by: default avatarMax Vozeler <xam@debian.org>
    Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
    Signed-off-by: default avatarVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
    Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
    1adcaafe
pgtable.h 15.2 KB