• Vladimir Oltean's avatar
    net: dsa: sja1105: Take PTP egress timestamp by port, not mgmt slot · 9fcf024d
    Vladimir Oltean authored
    The PTP egress timestamp N must be captured from register PTPEGR_TS[n],
    where n = 2 * PORT + TSREG. There are 10 PTPEGR_TS registers, 2 per
    port. We are only using TSREG=0.
    
    As opposed to the management slots, which are 4 in number
    (SJA1105_NUM_PORTS, minus the CPU port). Any management frame (which
    includes PTP frames) can be sent to any non-CPU port through any
    management slot. When the CPU port is not the last port (#4), there will
    be a mismatch between the slot and the port number.
    
    Luckily, the only mainline occurrence with this switch
    (arch/arm/boot/dts/ls1021a-tsn.dts) does have the CPU port as #4, so the
    issue did not manifest itself thus far.
    
    Fixes: 47ed985e ("net: dsa: sja1105: Add logic for TX timestamping")
    Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    9fcf024d
sja1105_ptp.c 18.5 KB