• Will Deacon's avatar
    ARM: pmu: add support for interrupt-affinity property · 9fd85eb5
    Will Deacon authored
    Historically, the PMU devicetree bindings have expected SPIs to be
    listed in order of *logical* CPU number. This is problematic for
    bootloaders, especially when the boot CPU (logical ID 0) isn't listed
    first in the devicetree.
    
    This patch adds a new optional property, interrupt-affinity, to the
    PMU node which allows the interrupt affinity to be described using
    a list of phandled to CPU nodes, with each entry in the list
    corresponding to the SPI at the same index in the interrupts property.
    
    Cc: Mark Rutland <mark.rutland@arm.com>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    9fd85eb5
perf_event_cpu.c 10.2 KB