• Mengdong Lin's avatar
    ALSA: hda - restore BCLK M/N values when resuming HSW/BDW display controller · a07187c9
    Mengdong Lin authored
    For Intel Haswell/Broadwell display HD-A controller, the 24MHz HD-A link BCLK
    is converted from Core Display Clock (CDCLK): BCLK = CDCLK * M / N
    And there are two registers EM4 and EM5 to program M, N value respectively.
    The EM4/EM5 values will be lost and when the display power well is disabled.
    
    BIOS programs CDCLK selected by OEM and EM4/EM5, but BIOS has no idea about
    display power well on/off at runtime. So the M/N can be wrong if non-default
    CDCLK is used when the audio controller resumes, which results in an invalid
    BCLK and abnormal audio playback rate. So this patch saves and restores valid
    M/N values on controller suspend/resume.
    
    And 'struct hda_intel' is defined to contain standard HD-A 'struct azx' and
    Intel specific fields, as Takashi suggested.
    Signed-off-by: default avatarMengdong Lin <mengdong.lin@intel.com>
    Cc: <stable@vger.kernel.org>
    Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
    a07187c9
hda_intel.c 54 KB