• Chris Wilson's avatar
    drm/i915: Use Write-Through cacheing for the display plane on Iris · 651d794f
    Chris Wilson authored
    Haswell GT3e has the unique feature of supporting Write-Through cacheing
    of objects within the eLLC/LLC. The purpose of this is to enable the display
    plane to remain coherent whilst objects lie resident in the eLLC/LLC - so
    that we, in theory, get the best of both worlds, perfect display and fast
    access.
    
    However, we still need to be careful as the CPU does not see the WT when
    accessing the cache. In particular, this means that we need to flush the
    cache lines after writing to an object through the CPU, and on
    transitioning from a cached state to WT.
    
    v2: Actually do the clflush on transition to WT, nagging by Ville.
    v3: Flush the CPU cache after writes into WT objects.
    v4: Rease onto LLC updates and report WT as "uncached" for
    get_cache_level_ioctl to remain symmetric with set_cache_level_ioctl.
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Cc: Kenneth Graunke <kenneth@whitecape.org>
    Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    651d794f
i915_drm.h 32.1 KB