• Markos Chandras's avatar
    MIPS: Make use of the ERETNC instruction on MIPS R6 · 7c151d3d
    Markos Chandras authored
    The ERETNC instruction, introduced in MIPS R5, is similar to the ERET
    one, except it does not clear the LLB bit in the LLADDR register.
    This feature is necessary to safely emulate R2 LL/SC instructions.
    However, on context switches, we need to clear the LLAddr/LLB bit
    in order to make sure that an SC instruction from the new thread
    will never succeed if it happens to interrupt an LL operation on the
    same address from the previous thread.
    Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
    7c151d3d
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