• James Hogan's avatar
    MIPS: perf: Allow sharing IRQ with timer · a1ec0e18
    James Hogan authored
    When requesting the performance counter overflow interrupt, pass flags
    which are compatible with the cevt-r4k driver, in particular
    IRQF_SHARED so that the two handlers can share the same IRQ. This is
    possible since release 2 of the architecture where there are separate
    pending interrupt bits for the timer interrupt and the performance
    counter interrupt.
    
    This will be necessary since the FDC interrupt can also be arbitrarily
    routed to a CPU interrupt, possibly sharing with the timer, the
    performance counters, or both, and it isn't scalable to have all the
    handlers able to call other handlers that may be on the same IRQ line.
    
    Shared handlers must also have a unique device pointer so they can be
    individually removed, so &mipspmu is now passed in for that instead of
    NULL.
    Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
    Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
    Cc: Ingo Molnar <mingo@redhat.com>
    Cc: Paul Mackerras <paulus@samba.org>
    Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
    Cc: linux-mips@linux-mips.org
    Cc: linux-kernel@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/9129/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    a1ec0e18
perf_event_mipsxx.c 43.5 KB