• David S. Miller's avatar
    sparc64: Use cpu_pgsz_mask for linear kernel mapping config. · c69ad0a3
    David S. Miller authored
    This required a little bit of reordering of how we set up the memory
    management early on.
    
    We now only know the final values of kern_linear_pte_xor[] after we
    take over the trap table and start processing TLB misses ourselves.
    
    So once we fill those values in we re-clear the kernel's 4M TSB and
    flush the TLBs.  That way if we find we support larger than 4M pages
    we won't have any stale smaller page size entries in the TSB.
    
    SUN4U Panther support for larger page sizes should now be extremely
    trivial but I have no hardware on which to test it and I believe
    that some of the sun4u TLB miss assembler needs to be audited first
    to make sure it really can handle larger than 4M PTEs properly.
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    c69ad0a3
init_64.c 60.7 KB