• Masahisa Kojima's avatar
    net: socionext: Add dummy PHY register read in phy_write() · a3241a91
    Masahisa Kojima authored
    There is a compatibility issue between RTL8211E implemented
    in Developerbox and netsec ethernet controller IP.
    
    Our MDIO controller stops MDC clock right after the write
    access, but RTL8211E expects MDC clock must be kept toggling
    for several clock cycle with MDIO high before entering
    the IDLE state. Without keeping clock after write access,
    write access is not correctly handled and register is not
    updated.
    
    To meet this requirement, netsec driver needs to issue dummy
    read(e.g. read PHYID1(offset 0x2) register) right after write
    access, to keep MDC clock.
    
    We think this compatibility issue is a problem specific to
    our MDIO controller and RTL8211E.
    
    Fixes: 533dd11a ("net: socionext: Add Synquacer NetSec driver")
    Signed-off-by: default avatarMasahisa Kojima <masahisa.kojima@linaro.org>
    Signed-off-by: default avatarYoshitoyo Osaki <osaki.yoshitoyo@socionext.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    a3241a91
netsec.c 45.3 KB