• Maciej W. Rozycki's avatar
    MIPS: Fix assembly error from MIPSr2 code used within MIPS_ISA_ARCH_LEVEL · a923a267
    Maciej W. Rozycki authored
    Fix assembly errors like:
    
    {standard input}: Assembler messages:
    {standard input}:287: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32'
    {standard input}:680: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32'
    {standard input}:1274: Error: opcode not supported on this processor: mips3 (mips3) `dins $12,$9,32,32'
    {standard input}:2175: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32'
    make[1]: *** [scripts/Makefile.build:277: mm/highmem.o] Error 1
    
    with code produced from `__cmpxchg64' for MIPS64r2 CPU configurations
    using CONFIG_32BIT and CONFIG_PHYS_ADDR_T_64BIT.
    
    This is due to MIPS_ISA_ARCH_LEVEL downgrading the assembly architecture
    to `r4000' i.e. MIPS III for MIPS64r2 configurations, while there is a
    block of code containing a DINS MIPS64r2 instruction conditionalized on
    MIPS_ISA_REV >= 2 within the scope of the downgrade.
    
    The assembly architecture override code pattern has been put there for
    LL/SC instructions, so that code compiles for configurations that select
    a processor to build for that does not support these instructions while
    still providing run-time support for processors that do, dynamically
    switched by non-constant `cpu_has_llsc'.  It went in with linux-mips.org
    commit aac8aa77 ("Enable a suitable ISA for the assembler around
    ll/sc so that code builds even for processors that don't support the
    instructions. Plus minor formatting fixes.") back in 2005.
    
    Fix the problem by wrapping these instructions along with the adjacent
    SYNC instructions only, following the practice established with commit
    cfd54de3 ("MIPS: Avoid move psuedo-instruction whilst using
    MIPS_ISA_LEVEL") and commit 378ed6f0 ("MIPS: Avoid using .set mips0
    to restore ISA").  Strictly speaking the SYNC instructions do not have
    to be wrapped as they are only used as a Loongson3 erratum workaround,
    so they will be enabled in the assembler by default, but do this so as
    to keep code consistent with other places.
    Reported-by: default avatarkernel test robot <lkp@intel.com>
    Signed-off-by: default avatarMaciej W. Rozycki <macro@orcam.me.uk>
    Fixes: c7e2d71d ("MIPS: Fix set_pte() for Netlogic XLR using cmpxchg64()")
    Cc: stable@vger.kernel.org # v5.1+
    Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
    a923a267
cmpxchg.h 8.67 KB