The Keystone 2 66AK2L SoCs have 4 TMS320C66x DSP Core Subsystems
(C66x CorePacs), each with a 1.0 GHz or 1.2 GHz C66x Fixed /
Floating-Point DSP Core, and 32 KB of L1P & L1D SRAMs and a 1 MB
L2 SRAM. Add the DT nodes for these DSP processor sub-systems.
The processors do not have an MMU, and use various IPC Generation
registers and shared memory for inter-processor communication.
The aliases with a stem 'rproc' have also been added for all the
DSPs, they provide a fixed remoteproc id to each DSP processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Sam Nelson <sam.nelson@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>