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Richard Leitner authored
Some PHYs need the refclk to be a continuous clock. Therefore they don't allow turning it off and on again during operation. Nonetheless such a clock switching is performed by some ETH drivers (namely FEC [1]) for power saving reasons. An example for an affected PHY is the SMSC/Microchip LAN8720 in "REF_CLK In Mode". In order to provide a uniform method to overcome this problem this patch adds a new phy_driver flag (PHY_RST_AFTER_CLK_EN) and corresponding function phy_reset_after_clk_enable() to the phylib. These should be used to trigger reset of the PHY after the refclk is switched on again. [1] commit e8fcfcd5 ("net: fec: optimize the clock management to save power") Signed-off-by:
Richard Leitner <richard.leitner@skidata.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
David S. Miller <davem@davemloft.net>
a9668491