• Kan Liang's avatar
    perf/x86/intel: Support branch counters logging · 33744916
    Kan Liang authored
    The branch counters logging (A.K.A LBR event logging) introduces a
    per-counter indication of precise event occurrences in LBRs. It can
    provide a means to attribute exposed retirement latency to combinations
    of events across a block of instructions. It also provides a means of
    attributing Timed LBR latencies to events.
    
    The feature is first introduced on SRF/GRR. It is an enhancement of the
    ARCH LBR. It adds new fields in the LBR_INFO MSRs to log the occurrences
    of events on the GP counters. The information is displayed by the order
    of counters.
    
    The design proposed in this patch requires that the events which are
    logged must be in a group with the event that has LBR. If there are
    more than one LBR group, the counters logging information only from the
    current group (overflowed) are stored for the perf tool, otherwise the
    perf tool cannot know which and when other groups are scheduled
    especially when multiplexing is triggered. The user can ensure it uses
    the maximum number of counters that support LBR info (4 by now) by
    making the group large enough.
    
    The HW only logs events by the order of counters. The order may be
    different from the order of enabling which the perf tool can understand.
    When parsing the information of each branch entry, convert the counter
    order to the enabled order, and store the enabled order in the extension
    space.
    
    Unconditionally reset LBRs for an LBR event group when it's deleted. The
    logged counter information is only valid for the current LBR group. If
    another LBR group is scheduled later, the information from the stale
    LBRs would be otherwise wrongly interpreted.
    
    Add a sanity check in intel_pmu_hw_config(). Disable the feature if other
    counter filters (inv, cmask, edge, in_tx) are set or LBR call stack mode
    is enabled. (For the LBR call stack mode, we cannot simply flush the
    LBR, since it will break the call stack. Also, there is no obvious usage
    with the call stack mode for now.)
    
    Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't require any branch
    stack setup.
    
    Expose the maximum number of supported counters and the width of the
    counters into the sysfs. The perf tool can use the information to parse
    the logged counters in each branch.
    Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
    Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
    Link: https://lkml.kernel.org/r/20231025201626.3000228-5-kan.liang@linux.intel.com
    33744916
lbr.c 43.9 KB