• Rob Herring's avatar
    PCI: dwc: Move N_FTS setup to common setup · aeaa0bfe
    Rob Herring authored
    The Designware controller has common registers to set number of fast
    training sequence ordered sets. The Artpec6, Intel, and Tegra driver
    initialize these register fields. Let's move the initialization to the
    common setup code and drivers just have to provide the value.
    
    There's a slight change in that the common clock mode N_FTS field is
    now initialized. Previously only the Intel driver set this. It's not
    clear from the code if common clock mode is used in the Artpec6 or Tegra
    driver. It depends on the DWC configuration. Given the field is not
    initialized while the others are, it seems unlikely common clock mode
    is used.
    
    Link: https://lore.kernel.org/r/20200821035420.380495-40-robh@kernel.orgSigned-off-by: default avatarRob Herring <robh@kernel.org>
    Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Jesper Nilsson <jesper.nilsson@axis.com>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Bjorn Helgaas <bhelgaas@google.com>
    Cc: Jingoo Han <jingoohan1@gmail.com>
    Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    Cc: Thierry Reding <thierry.reding@gmail.com>
    Cc: Jonathan Hunter <jonathanh@nvidia.com>
    Cc: linux-tegra@vger.kernel.org
    aeaa0bfe
pcie-tegra194.c 63 KB