We can shrink the pagevec structure to cacheline align it.  It is used all
over VM reclaiming and mpage pagecache read code.

Right now it is 140 bytes on 64-bit and 72 bytes on 32-bit.  Thats just a
little bit more than a power of 2 (which will cacheline align), so shrink
it to be aligned: 64 bytes on 32bit and 124bytes on 64-bit. 

It now occupies two cachelines most of the time instead of three. 

I changed nr and cold to "unsigned short" because they'll never reach 2 ^ 16.

Did some reaim benchmarking on 4way PIII (32byte cacheline), with 512MB RAM:

#### stock 2.6.9-rc1-mm4 ####

Peak load Test: Maximum Jobs per Minute 4144.44 (average of 3 runs)
Quick Convergence Test: Maximum Jobs per Minute 4007.86 (average of 3 runs)

Peak load Test: Maximum Jobs per Minute 4207.48 (average of 3 runs)
Quick Convergence Test: Maximum Jobs per Minute 3999.28 (average of 3 runs)

#### shrink-pagevec #####

Peak load Test: Maximum Jobs per Minute 4717.88 (average of 3 runs)
Quick Convergence Test: Maximum Jobs per Minute 4360.59 (average of 3 runs)

Peak load Test: Maximum Jobs per Minute 4493.18 (average of 3 runs)
Quick Convergence Test: Maximum Jobs per Minute 4327.77 (average of 3 runs)
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>