• Arunpravin Paneer Selvam's avatar
    drm/amd/amdgpu: Enable high priority gfx queue · b07d1d73
    Arunpravin Paneer Selvam authored
    Starting from SIENNA CICHLID asic supports two gfx pipes, enabling
    two graphics queues, 1 on each pipe, pipe0 queue0 would be the normal
    piority queue and pipe1 queue0 would be the high priority queue
    
    Only one queue per pipe is visble to SPI, SPI looks at the priority
    value assigned to CP_GFX_HQD_QUEUE_PRIORITY from each of the queue's
    HQD/MQD.
    
    Create contexts applying AMDGPU_CTX_PRIORITY_HIGH which submits job
    to the high priority queue on GFX pipe1. There would be starvation
    of LP workload if HP workload is always available.
    
    v2:
      - remove unnecessary check(Nirmoy)
      - make pipe1 hardware support a separate patch(Nirmoy)
      - remove duplicate code(Shashank)
      - add CSA support for second gfx pipe(Alex)
    
    v3(Christian):
      - fix incorrect indentation
      - merge COMPUTE and GFX switch cases as both calls the same function.
    
    v4:
      - rebase w/ latest code base
    Signed-off-by: default avatarArunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
    Acked-by: default avatarChristian König <christian.koenig@amd.com>
    Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
    b07d1d73
amdgpu_ring.c 15.6 KB