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Masahiro Yamada authored
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings document says that the bits[15:8] of the 3rd cell of the interrupts property represents PPI interrupt CPU mask. Because the timer interrupts are wired to all of the 4 cores, bits[15:8] should be set to 0xf. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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