• Rodrigo Vivi's avatar
    drm/i915: Disable caches for Global GTT. · d6a8b72e
    Rodrigo Vivi authored
    Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
    So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
    
    MOCS can still be used though. But if userspace is trusting PTE for
    cache selection the safest thing to do is to let caches disabled.
    
    BSpec: "For GGTT, there is NO pat_sel[2:0] from the entry,
    so RTL will always use the value corresponding to pat_sel = 000"
    
    - System agent ggtt writes (i.e. cpu gtt mmaps) already work before
    this patch, i.e. the same uncached + snooping access like on gen6/7
    seems to be in effect.
    - So this just fixes blitter/render access. Again it looks like it's
    not just uncached access, but uncached + snooping. So we can still
    hold onto all our assumptions wrt cpu clflushing on LLC machines.
    
    v2: Cleaner patch as suggested by Chris.
    v3: Add Daniel's comment
    
    Reference: https://bugs.freedesktop.org/show_bug.cgi?id=85576
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: James Ausmus <james.ausmus@intel.com>
    Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
    Cc: Jani Nikula <jani.nikula@intel.com>
    Cc: Stable@vger.kernel.org
    Tested-by: default avatarJames Ausmus <james.ausmus@intel.com>
    Reviewed-by: default avatarJames Ausmus <james.ausmus@intel.com>
    Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
    d6a8b72e
i915_gem_gtt.c 56.9 KB