• Laurent Pinchart's avatar
    drm: rcar-du: Use LVDS PLL clock as dot clock when possible · b4734f43
    Laurent Pinchart authored
    On selected SoCs, the DU can use the clock output by the LVDS encoder
    PLL as its input dot clock. This feature is optional, but on the D3 and
    E3 SoC it is often the only way to obtain a precise dot clock frequency,
    as the other available clocks (CPG-generated clock and external clock)
    usually have fixed rates.
    
    Add a DU model information field to describe which DU channels can use
    the LVDS PLL output clock as their input clock, and configure clock
    routing accordingly.
    
    This feature is available on H2, M2-W, M2-N, D3 and E3 SoCs, with D3 and
    E3 being the primary targets. It is left disabled in this commit, and
    will be enabled per-SoC after careful testing.
    
    At the hardware level, clock routing is configured at runtime in two
    steps, first selecting an internal dot clock between the LVDS PLL clock
    and the external DOTCLKIN clock, and then selecting between the internal
    dot clock and the CPG-generated clock. The first part requires stopping
    the whole DU group in order for the change to take effect, thus causing
    flickering on the screen. For this reason we currently hardcode the
    clock source to the LVDS PLL clock if available, and allow flicker-free
    selection of the external DOTCLKIN clock or CPG-generated clock
    otherwise. A more dynamic clock selection process can be implemented
    later if the need arises.
    Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
    Tested-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
    Reviewed-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
    b4734f43
rcar_du_crtc.c 30.3 KB