• WANG Xuerui's avatar
    MIPS: handle Loongson-specific GSExc exception · bc6e8dc1
    WANG Xuerui authored
    Newer Loongson cores (Loongson-3A R2 and newer) use the
    implementation-dependent ExcCode 16 to signal Loongson-specific
    exceptions. The extended cause is put in the non-standard CP0.Diag1
    register which is CP0 Register 22 Select 1, called GSCause in Loongson
    manuals. Inside is an exception code bitfield called GSExcCode, only
    codes 0 to 6 inclusive are documented (so far, in the Loongson 3A3000
    User Manual, Volume 2).
    
    During experiments, it was found that some undocumented unprivileged
    instructions can trigger the also-undocumented GSExcCode 8 on Loongson
    3A4000. Processor state is not corrupted, but we cannot continue without
    further knowledge, and Loongson is not providing that information as of
    this writing. So we send SIGILL on seeing this exception code to thwart
    easy local DoS attacks.
    
    Other exception codes are made fatal, partly because of insufficient
    knowledge, also partly because they are not as easily reproduced. None
    of them are encountered in the wild with upstream kernels and userspace
    so far.
    
    Some older cores (Loongson-3A1000 and Loongson-3B1500) have ExcCode 16
    too, but the semantic is equivalent to GSExcCode 0. Because the
    respective manuals did not mention the CP0.Diag1 register or its read
    behavior, these cores are not covered in this patch, as MFC0 from
    non-existent CP0 registers is UNDEFINED according to the MIPS
    architecture spec.
    Reviewed-by: default avatarHuacai Chen <chenhc@lemote.com>
    Signed-off-by: default avatarWANG Xuerui <git@xen0n.name>
    Cc: Huacai Chen <chenhc@lemote.com>
    Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
    Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
    Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
    bc6e8dc1
cpu-probe.c 62 KB