• Vineet Gupta's avatar
    ARCv2: barriers · b8a03302
    Vineet Gupta authored
    ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for
    kernel proper.
    
    SMP barrier is provided by DMB instruction which also guarantees local
    barrier hence used as backend of smp_*mb() as well as *mb() APIs
    
    Also hookup barriers into MMIO accessors to avoid ordering issues in IO
    
    Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
    Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
    Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
    b8a03302
barrier.h 1.51 KB