• Richard Watts's avatar
    clk: ti: omap36xx: Work around sprz319 advisory 2.1 · 035cd485
    Richard Watts authored
    The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term
    frequency drift. The frequency drift magnitude depends on the VCO update
    rate, which is inversely proportional to the PLL divider. The kernel
    DPLL configuration code results in a high value for the divider, leading
    to a long term drift high enough to cause USB transmission errors. In
    the worst case the USB PHY's ULPI interface can stop responding,
    breaking USB operation completely. This manifests itself on the
    Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the
    cable is bad?' in the kernel log.
    
    Errata sprz319 advisory 2.1 documents PLL values that minimize the
    drift. Use them automatically when DPLL5 is used for USB operation,
    which we detect based on the requested clock rate. The clock framework
    will still compute the PLL parameters and resulting rate as usual, but
    the PLL M and N values will then be overridden. This can result in the
    effective clock rate being slightly different than the rate cached by
    the clock framework, but won't cause any adverse effect to USB
    operation.
    Signed-off-by: default avatarRichard Watts <rrw@kynesim.co.uk>
    [Upported from v3.2 to v4.9]
    Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
    Tested-by: default avatarLadislav Michl <ladis@linux-mips.org>
    Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
    035cd485
clock.h 7.83 KB