• Shreyas B. Prabhu's avatar
    cpuidle/powernv: Add support for POWER ISA v3 idle states · 3005c597
    Shreyas B. Prabhu authored
    POWER ISA v3 defines a new idle processor core mechanism. In summary,
     a) new instruction named stop is added.
     b) new per thread SPR named PSSCR is added which controls the behavior
    	of stop instruction.
    
    Supported idle states and value to be written to PSSCR register to enter
    any idle state is exposed via ibm,cpu-idle-state-names and
    ibm,cpu-idle-state-psscr respectively. To enter an idle state,
    platform provided power_stop() needs to be invoked with the appropriate
    PSSCR value.
    
    This patch adds support for this new mechanism in cpuidle powernv driver.
    
    Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
    Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
    Cc: Rob Herring <robh+dt@kernel.org>
    Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>
    Cc: linux-pm@vger.kernel.org
    Cc: Michael Ellerman <mpe@ellerman.id.au>
    Cc: Paul Mackerras <paulus@ozlabs.org>
    Cc: linuxppc-dev@lists.ozlabs.org
    Reviewed-by: default avatarGautham R. Shenoy <ego@linux.vnet.ibm.com>
    Signed-off-by: default avatarShreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    3005c597
cpuidle-powernv.c 9.09 KB