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Icenowy Zheng authored
The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by:
Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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