• Huacai Chen's avatar
    MIPS: Loongson: Add basic Loongson-3 definition · 152ebb44
    Huacai Chen authored
    Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully.
    Loongson-3 has the same IMP field (0x6300) as Loongson-2.
    
    Loongson-3 has a hardware-maintained cache, system software doesn't
    need to maintain coherency.
    
    Loongson-3A is the first revision of Loongson-3, and it is the quad-
    core version of Loongson-2G. Loongson-3A has a simplified version named
    Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two
    HyperTransport controller but 2Gq has only one. HT0 is used for cross-
    chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq
    cannot support NUMA but 3A can. For software, Loongson-2Gq is simply
    identified as Loongson-3A.
    
    Exsisting Loongson family CPUs:
    Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs.
    Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit
                single-core MIPS CPUs.
    Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are
                64-bit multi-core MIPS CPUs.
    Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
    Signed-off-by: default avatarHongliang Tao <taohl@lemote.com>
    Signed-off-by: default avatarHua Yan <yanh@lemote.com>
    Tested-by: default avatarAlex Smith <alex.smith@imgtec.com>
    Reviewed-by: default avatarAlex Smith <alex.smith@imgtec.com>
    Cc: John Crispin <john@phrozen.org>
    Cc: Steven J. Hill <Steven.Hill@imgtec.com>
    Cc: Aurelien Jarno <aurelien@aurel32.net>
    Cc: linux-mips@linux-mips.org
    Cc: Fuxin Zhang <zhangfx@lemote.com>
    Cc: Zhangjin Wu <wuzhangjin@gmail.com>
    Patchwork: https://patchwork.linux-mips.org/patch/6629/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    152ebb44
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