• Christoph Hellwig's avatar
    riscv: provide native clint access for M-mode · fcdc6537
    Christoph Hellwig authored
    RISC-V has the concept of a cpu level interrupt controller.  The
    interface for it is split between a standardized part that is exposed
    as bits in the mstatus/sstatus register and the mie/mip/sie/sip
    CRS.  But the bit to actually trigger IPIs is not standardized and
    just mentioned as implementable using MMIO.
    
    Add support for IPIs using MMIO using the SiFive clint layout (which
    is also shared by Ariane, Kendryte and the Qemu virt platform).
    Additionally the MMIO block also supports the time value and timer
    compare registers, so they are also set up using the same OF node.
    Support for other layouts should also be relatively easy to add in the
    future.
    Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
    Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
    [paul.walmsley@sifive.com: update include guard format; fix checkpatch
     issues; minor commit message cleanup]
    Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
    fcdc6537
clint.c 945 Bytes