• Paul Mackerras's avatar
    powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live · c22435a5
    Paul Mackerras authored
    At present, the analyse_instr/emulate_step code checks for the
    relevant MSR_FP/VEC/VSX bit being set when a FP/VMX/VSX load
    or store is decoded, but doesn't recheck the bit before reading or
    writing the relevant FP/VMX/VSX register in emulate_step().
    
    Since we don't have preemption disabled, it is possible that we get
    preempted between checking the MSR bit and doing the register access.
    If that happened, then the registers would have been saved to the
    thread_struct for the current process.  Accesses to the CPU registers
    would then potentially read stale values, or write values that would
    never be seen by the user process.
    
    Another way that the registers can become non-live is if a page
    fault occurs when accessing user memory, and the page fault code
    calls a copy routine that wants to use the VMX or VSX registers.
    
    To fix this, the code for all the FP/VMX/VSX loads gets restructured
    so that it forms an image in a local variable of the desired register
    contents, then disables preemption, checks the MSR bit and either
    sets the CPU register or writes the value to the thread struct.
    Similarly, the code for stores checks the MSR bit, copies either the
    CPU register or the thread struct to a local variable, then reenables
    preemption and then copies the register image to memory.
    
    If the instruction being emulated is in the kernel, then we must not
    use the register values in the thread_struct.  In this case, if the
    relevant MSR enable bit is not set, then emulate_step refuses to
    emulate the instruction.
    Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    c22435a5
ldstfp.S 3.93 KB