• Alex Deucher's avatar
    drm/amdgpu/display: drop DCN support for aarch64 · c241ed2f
    Alex Deucher authored
    From Ard:
    
    "Simply disabling -mgeneral-regs-only left and right is risky, given that
    the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
    and GCC is known to use SIMD registers for spilling, and may invent
    other uses of the FP/SIMD register file that have nothing to do with the
    floating point code in question. Note that putting kernel_neon_begin()
    and kernel_neon_end() around the code that does use FP is not sufficient
    here, the problem is in all the other code that may be emitted with
    references to SIMD registers in it.
    
    So the only way to do this properly is to put all floating point code in
    a separate compilation unit, and only compile that unit with
    -mgeneral-regs-only."
    
    Disable support until the code can be properly refactored to support this
    properly on aarch64.
    Acked-by: default avatarWill Deacon <will@kernel.org>
    Reported-by: default avatarArd Biesheuvel <ardb@kernel.org>
    Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
    c241ed2f
dcn10_resource.c 42.6 KB