• Laurent Pinchart's avatar
    drm: rcar-du: lvds: D3/E3 support · c25c0136
    Laurent Pinchart authored
    The LVDS encoders in the D3 and E3 SoCs differ significantly from those
    in the other R-Car Gen3 family members:
    
    - The LVDS PLL architecture is more complex and requires computing PLL
      parameters manually.
    - The PLL uses external clocks as inputs, which need to be retrieved
      from DT.
    - In addition to the different PLL setup, the startup sequence has
      changed *again* (seems someone had trouble making his/her mind).
    
    Supporting all this requires DT bindings extensions for external clocks,
    brand new PLL setup code, and a few quirks to handle the differences in
    the startup sequence.
    
    The implementation doesn't support all hardware features yet, namely
    
    - Using the LV[01] clocks generated by the CPG as PLL input.
    - Providing the LVDS PLL clock to the DU for use with the RGB output.
    
    Those features can be added later when the need will arise.
    Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
    Tested-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
    Reviewed-by: default avatarUlrich Hecht <uli+renesas@fpond.eu>
    Reviewed-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
    c25c0136
rcar_lvds_regs.h 3.73 KB