• Masahiro Yamada's avatar
    pinctrl: uniphier: introduce capability flag · c2ebf475
    Masahiro Yamada authored
    The core part of the UniPhier pinctrl driver needs to support a new
    capability for upcoming UniPhier ARMv8 SoCs.  This sometimes happens
    because pinctrl drivers include really SoC-specific stuff.
    
    This commit intends to tidy up SoC-specific parameters of the existing
    drivers before adding the new one.  Having just one flag would be
    better than adding a new struct member every time a new SoC-specific
    capability comes up.
    
    At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
    This capability (I'd say rather quirk) was added for PH1-Pro4 and
    PH1-Pro5 as requirement from a customer.  For those SoCs, one pin-mux
    setting is controlled by the combination of two separate registers; the
    LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
    Because it is impossible to update two separate registers atomically,
    the LOAD_PINCTRL register should be set in order to make the pin-mux
    settings really effective.
    Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
    Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
    c2ebf475
pinctrl-uniphier-pxs2.c 56.5 KB