• Andy Shevchenko's avatar
    dmaengine: dw: rename masters to reflect actual topology · c422025c
    Andy Shevchenko authored
    The source and destination masters are reflecting buses or their layers to
    where the different devices can be connected. The patch changes the master
    names to reflect which one is related to which independently on the transfer
    direction.
    
    The outcome of the change is that the memory data width is now always limited
    by a data width of the master which is dedicated to communicate to memory.
    
    The patch will not break anything since all current users have the same data
    width for all masters. Though it would be nice to revisit avr32 platforms to
    check what is the actual hardware topology in use there. It seems that it has
    one bus and two masters on it as stated by Table 8-2, that's why everything
    works independently on the master in use. The purpose of the sequential patch
    is to fix the driver for configuration of more than one bus.
    
    The change is done in the assumption that src_master and dst_master are
    reflecting a connection to the memory and peripheral correspondently on avr32
    and otherwise on the rest.
    Acked-by: default avatarHans-Christian Egtvedt <egtvedt@samfundet.no>
    Acked-by: default avatarMark Brown <broonie@kernel.org>
    Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
    Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
    c422025c
spi-pxa2xx-pci.c 5.55 KB