• Luis R. Rodriguez's avatar
    ath9k_hw: update 5 GHz tx gain tables for femless and high power PA · 1cc5c4b5
    Luis R. Rodriguez authored
    This updates the initvals for AR9003 to adjust the 5 GHz tx gain
    tables for femless and high power PA.
    
    References:
    
    	Osprey 2.0 header file ver 72
    	Osprey 2.2 header file ver 20
    
    Checksums:
    
    $ ./initvals -f ar9003-2p0
    0x00000000c2bfa7d5        ar9300_2p0_radio_postamble
    0x00000000ada2b114        ar9300Modes_lowest_ob_db_tx_gain_table_2p0
    0x00000000e0bc2c84        ar9300Modes_fast_clock_2p0
    0x00000000056eaf74        ar9300_2p0_radio_core
    0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p0
    0x0000000078658fb5        ar9300_2p0_mac_postamble
    0x0000000023235333        ar9300_2p0_soc_postamble
    0x0000000054d41904        ar9200_merlin_2p0_radio_core
    0x00000000748572cf        ar9300_2p0_baseband_postamble
    0x000000009aa5a0a4        ar9300_2p0_baseband_core
    0x000000003dffa526        ar9300Modes_high_power_tx_gain_table_2p0
    0x000000001cfda724        ar9300Modes_high_ob_db_tx_gain_table_2p0
    0x0000000011302700        ar9300Common_rx_gain_table_2p0
    0x00000000e3eab114        ar9300Modes_low_ob_db_tx_gain_table_2p0
    0x00000000c9d66d40        ar9300_2p0_mac_core
    0x000000001e1d0800        ar9300Common_wo_xlna_rx_gain_table_2p0
    0x00000000a0c54980        ar9300_2p0_soc_preamble
    0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p0
    0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p0
    0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p0
    
    $ ./initvals -f ar9003-2p2
    0x00000000c2bfa7d5        ar9300_2p2_radio_postamble
    0x00000000ada2b114        ar9300Modes_lowest_ob_db_tx_gain_table_2p2
    0x00000000e0bc2c84        ar9300Modes_fast_clock_2p2
    0x00000000056eaf74        ar9300_2p2_radio_core
    0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p2
    0x0000000078658fb5        ar9300_2p2_mac_postamble
    0x0000000023235333        ar9300_2p2_soc_postamble
    0x0000000054d41904        ar9200_merlin_2p2_radio_core
    0x000000008475a084        ar9300_2p2_baseband_postamble
    0x000000009aaafd90        ar9300_2p2_baseband_core
    0x000000003dffa526        ar9300Modes_high_power_tx_gain_table_2p2
    0x000000001cfda724        ar9300Modes_high_ob_db_tx_gain_table_2p2
    0x0000000011302700        ar9300Common_rx_gain_table_2p2
    0x00000000a9a2b114        ar9300Modes_low_ob_db_tx_gain_table_2p2
    0x00000000a9d66d40        ar9300_2p2_mac_core
    0x000000001e1d0800        ar9300Common_wo_xlna_rx_gain_table_2p2
    0x00000000a0c531c8        ar9300_2p2_soc_preamble
    0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
    0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p2
    0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p2
    Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
    Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
    1cc5c4b5
ar9003_2p0_initvals.h 60.1 KB