• Majd Dibbiny's avatar
    IB/mlx5: Change TX affinity assignment in RoCE LAG mode · c6a21c38
    Majd Dibbiny authored
    In the current code, the TX affinity is per RoCE device, which can cause
    unfairness between different contexts. e.g. if we open two contexts, and
    each open 10 QPs concurrently, all of the QPs of the first context might
    end up on the first port instead of distributed on the two ports as
    expected
    
    To overcome this unfairness between processes, we maintain per device TX
    affinity, and per process TX affinity.
    
    The allocation algorithm is as follow:
    
    1. Hold two tx_port_affinity atomic variables, one per RoCE device and one
       per ucontext. Both initialized to 0.
    
    2. In mlx5_ib_alloc_ucontext do:
     2.1. ucontext.tx_port_affinity = device.tx_port_affinity
     2.2. device.tx_port_affinity += 1
    
    3. In modify QP INIT2RST:
     3.1. qp.tx_port_affinity = ucontext.tx_port_affinity % MLX5_PORT_NUM
     3.2. ucontext.tx_port_affinity += 1
    Signed-off-by: default avatarMajd Dibbiny <majd@mellanox.com>
    Reviewed-by: default avatarMoni Shoua <monis@mellanox.com>
    Signed-off-by: default avatarLeon Romanovsky <leonro@mellanox.com>
    Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
    c6a21c38
main.c 172 KB