• Ville Syrjälä's avatar
    drm/i915: Make sure PND deadline mode is enabled on VLV/CHV · c6beb13e
    Ville Syrjälä authored
    Poke at the CBR1_VLV register during init_clock_gating to make sure the
    PND deadline scheme is used.
    
    The hardware has two modes of operation wrt. watermarks:
    
    1) PND deadline mode:
     - memory request deadline is calculated from actual FIFO level * DDL
     - WM1 watermark values are unused (AFAIK)
     - WM watermark level defines when to start fetching data from memory
       (assuming trickle feed is not used)
    
    2) backup mode
     - deadline is based on FIFO status, DDL is unused
     - FIFO split into three regions with WM and WM1 watermarks, each
       part specifying a different FIFO status
    
    We want to use the PND deadline mode, so let's make sure the chicken
    bit is in the correct position on init.
    
    Also take the opportunity to refactor the shared code between VLV and
    CHV to a shared function.
    Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
    Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    c6beb13e
intel_pm.c 186 KB