• Stephane Eranian's avatar
    perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking · 6b89d4c1
    Stephane Eranian authored
    On Intel Westmere, a cmdline as follows:
    
      $ perf record -e cpu/event=0xc4,umask=0x2,name=br_inst_retired.near_call/p ....
    
    was failing. Yet the event+ umask support PEBS.
    
    It turns out this is due to a bug in the the PEBS event constraint table for
    westmere. All forms of BR_INST_RETIRED.* support PEBS. Therefore the constraint
    mask should ignore the umask. The name of the macro INTEL_FLAGS_EVENT_CONSTRAINT()
    hint that this is the case but it was not. That macros was checking both the
    event code and event umask. Therefore, it was only matching on 0x00c4.
    There are code+umask macros, they all have *UEVENT*.
    
    This bug fixes the issue by checking only the event code in the mask.
    Both single and range version are modified.
    Signed-off-by: default avatarStephane Eranian <eranian@google.com>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Cc: kan.liang@intel.com
    Link: http://lkml.kernel.org/r/20190509214556.123493-1-eranian@google.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    6b89d4c1
perf_event.h 30 KB