• John David Anglin's avatar
    parisc: Fix A500 boot crash · c9fa406f
    John David Anglin authored
    I believe the following change will fix the cache/TLB inconsistency
    observed by Meelis.  After changing the page table entries, we need to
    flush the cache and TLB to ensure that we don't have any stale PTE
    values in the cache or TLB.
    
    The alternative patching is done after all CPUs are running.  Thus, we
    need to flush the whole cache and TLB.
    
    I included the init section in the range modified by map_pages as
    suggested by Helge.  Some routines in the init section may require
    patching.
    Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
    Signed-off-by: default avatarHelge Deller <deller@gmx.de>
    c9fa406f
init.c 24.3 KB