• Mark Yao's avatar
    drm/rockchip: Optimization vop mode set · ce3887ed
    Mark Yao authored
    Rk3288 vop timing registers is immediately register, when configure
    timing on display active time, will cause tearing. use dclk reset is
    not a good idea to avoid this tearing. we can avoid tearing by using
    standby register.
    
    Vop standby register will take effect at end of current frame, and
    go back to work immediately when exit standby.
    
    So we can use standby register to protect this context.
    Signed-off-by: default avatarMark Yao <mark.yao@rock-chips.com>
    ce3887ed
rockchip_drm_vop.c 42.5 KB