• Zhenyu Ye's avatar
    arm64: tlb: Use the TLBI RANGE feature in arm64 · d1d3aa98
    Zhenyu Ye authored
    Add __TLBI_VADDR_RANGE macro and rewrite __flush_tlb_range().
    
    When cpu supports TLBI feature, the minimum range granularity is
    decided by 'scale', so we can not flush all pages by one instruction
    in some cases.
    
    For example, when the pages = 0xe81a, let's start 'scale' from
    maximum, and find right 'num' for each 'scale':
    
    1. scale = 3, we can flush no pages because the minimum range is
       2^(5*3 + 1) = 0x10000.
    2. scale = 2, the minimum range is 2^(5*2 + 1) = 0x800, we can
       flush 0xe800 pages this time, the num = 0xe800/0x800 - 1 = 0x1c.
       Remaining pages is 0x1a;
    3. scale = 1, the minimum range is 2^(5*1 + 1) = 0x40, no page
       can be flushed.
    4. scale = 0, we flush the remaining 0x1a pages, the num =
       0x1a/0x2 - 1 = 0xd.
    
    However, in most scenarios, the pages = 1 when flush_tlb_range() is
    called. Start from scale = 3 or other proper value (such as scale =
    ilog2(pages)), will incur extra overhead.
    So increase 'scale' from 0 to maximum, the flush order is exactly
    opposite to the example.
    Signed-off-by: default avatarZhenyu Ye <yezhenyu2@huawei.com>
    Link: https://lore.kernel.org/r/20200715071945.897-4-yezhenyu2@huawei.com
    [catalin.marinas@arm.com: removed unnecessary masks in __TLBI_VADDR_RANGE]
    [catalin.marinas@arm.com: __TLB_RANGE_NUM subtracts 1]
    [catalin.marinas@arm.com: minor adjustments to the comments]
    [catalin.marinas@arm.com: introduce system_supports_tlb_range()]
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    d1d3aa98
cpufeature.h 25 KB