• Maxime Ripard's avatar
    clk: sunxi: display: Add per-clock flags · 07ea0b4d
    Maxime Ripard authored
    The TCON channel 0 clock that is the parent clock of our pixel clock is
    expected to change its rate depending on the resolution we want to output
    in our display engine.
    
    However, since it's only a mux, the only way it can do that is by changing
    its parents rate.
    
    Allow to give flags in our display clocks description, and add the
    CLK_SET_RATE_PARENT flag for the TCON channel 0 flag.
    
    Fixes: a3b4956ee6d9 ("clk: sunxi: display: Add per-clock flags")
    Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
    Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
    07ea0b4d
clk-sun4i-display.c 6.27 KB