• Kan Liang's avatar
    perf/x86/intel: Add perf core PMU support for Sapphire Rapids · 61b985e3
    Kan Liang authored
    Add perf core PMU support for the Intel Sapphire Rapids server, which is
    the successor of the Intel Ice Lake server. The enabling code is based
    on Ice Lake, but there are several new features introduced.
    
    The event encoding is changed and simplified, e.g., the event codes
    which are below 0x90 are restricted to counters 0-3. The event codes
    which above 0x90 are likely to have no restrictions. The event
    constraints, extra_regs(), and hardware cache events table are changed
    accordingly.
    
    A new Precise Distribution (PDist) facility is introduced, which
    further minimizes the skid when a precise event is programmed on the GP
    counter 0. Enable the Precise Distribution (PDist) facility with :ppp
    event. For this facility to work, the period must be initialized with a
    value larger than 127. Add spr_limit_period() to apply the limit for
    :ppp event.
    
    Two new data source fields, data block & address block, are added in the
    PEBS Memory Info Record for the load latency event. To enable the
    feature,
    - An auxiliary event has to be enabled together with the load latency
      event on Sapphire Rapids. A new flag PMU_FL_MEM_LOADS_AUX is
      introduced to indicate the case. A new event, mem-loads-aux, is
      exposed to sysfs for the user tool.
      Add a check in hw_config(). If the auxiliary event is not detected,
      return an unique error -ENODATA.
    - The union perf_mem_data_src is extended to support the new fields.
    - Ice Lake and earlier models do not support block information, but the
      fields may be set by HW on some machines. Add pebs_no_block to
      explicitly indicate the previous platforms which don't support the new
      block fields. Accessing the new block fields are ignored on those
      platforms.
    
    A new store Latency facility is introduced, which leverages the PEBS
    facility where it can provide additional information about sampled
    stores. The additional information includes the data address, memory
    auxiliary info (e.g. Data Source, STLB miss) and the latency of the
    store access. To enable the facility, the new event (0x02cd) has to be
    programed on the GP counter 0. A new flag PERF_X86_EVENT_PEBS_STLAT is
    introduced to indicate the event. The store_latency_data() is introduced
    to parse the memory auxiliary info.
    
    The layout of access latency field of PEBS Memory Info Record has been
    changed. Two latency, instruction latency (bit 15:0) and cache access
    latency (bit 47:32) are recorded.
    - The cache access latency is similar to previous memory access latency.
      For loads, the latency starts by the actual cache access until the
      data is returned by the memory subsystem.
      For stores, the latency starts when the demand write accesses the L1
      data cache and lasts until the cacheline write is completed in the
      memory subsystem.
      The cache access latency is stored in low 32bits of the sample type
      PERF_SAMPLE_WEIGHT_STRUCT.
    - The instruction latency starts by the dispatch of the load operation
      for execution and lasts until completion of the instruction it belongs
      to.
      Add a new flag PMU_FL_INSTR_LATENCY to indicate the instruction
      latency support. The instruction latency is stored in the bit 47:32
      of the sample type PERF_SAMPLE_WEIGHT_STRUCT.
    
    Extends the PERF_METRICS MSR to feature TMA method level 2 metrics. The
    lower half of the register is the TMA level 1 metrics (legacy). The
    upper half is also divided into four 8-bit fields for the new level 2
    metrics. Expose all eight Topdown metrics events to user space.
    
    The full description for the SPR features can be found at Intel
    Architecture Instruction Set Extensions and Future Features
    Programming Reference, 319433-041.
    Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
    Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
    Link: https://lkml.kernel.org/r/1611873611-156687-5-git-send-email-kan.liang@linux.intel.com
    61b985e3
ds.c 60.8 KB