• Shawn Guo's avatar
    ARM: imx: ensure dsm_request signal is not asserted when setting LPM · d48866fe
    Shawn Guo authored
    There is a defect in imx6 LPM design.  When SW tries to enter low power
    mode with following sequence, the chip will enter low power mode before
    A9 CPU execute WFI instruction:
    
    1. Set CCM_CLPCR[1:0] to 2'b00;
    2. ARM CPU enters WFI;
    3. ARM CPU wakeup from an interrupt event, which is masked by GPC or not
       visible to GPC, such as interrupt from local timer;
    4. Set CCM_CLPCR[1:0] to 2'b01 or 2'b10;
    5. ARM CPU execute WFI.
    
    Before the last step, the chip will enter WAIT mode if CCM_CLPCR[1:0] is
    set to 2'b01, or enter STOP mode if CCM_CLPCR[1:0] is set to 2'b10.
    
    The patch implements a recommended workaround for this issue.
    
    1. SW triggers irq #32(IOMUX) to be always pending manually by setting
       IOMUX_GPR1_GINT bit;
    2. SW should then unmask it in GPC before setting CCM LPM;
    3. SW should mask it right after CCM LPM is set (bit0-1 of CCM_CLPCR).
    Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
    d48866fe
gpc.c 3.07 KB