DSI specific RCG clocks required customized clk_ops. There are
a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL.

There are a total of 2 clocks coming from the DSI PLL, which serve as
inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the
post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by
another divider of the PLL.

In each of the 2 groups above, only one of the clocks sets its parent.
These are BYTE RCG and DSI RCG for each of the groups respectively, as
shown in the diagram below.

The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops
clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't
take in a freq table, since the DSI driver using these clocks is
parent-able.

The PIXEL RCG needs to derive the required pixel clock using dsixpll.
It parses a m/n frac table to retrieve the correct clock.

The ESC RCG doesn't have a frac M/N block, it can just apply a pre-
divider. Its ops simply check if the required clock rate can be
achieved by the pre-divider.

      +-------------------+
      |                   |---dsixpllbyte---o---> To byte RCG
      |                   |                 | (sets parent rate)
      |                   |                 |
      |                   |                 |
      |    DSI 1/2 PLL    |                 |
      |                   |                 o---> To esc RCG
      |                   |                 (doesn't set parent rate)
      |                   |
      |                   |----dsixpll-----o---> To dsi RCG
      +-------------------+                | (sets parent rate)
                             ( x = 1, 2 )  |
                                           |
                                           o---> To pixel rcg
                                           (doesn't set parent rate)
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>